How processors can be classified? This post will briefly discuss about the differences between two popular mainstream architectures and how they are differentiate: RISC vs CISC. Both have their respective advantages and shortages with different tasks. It's their approach into handling information that separates and diverges how they construct a microprocessor.
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The Instruction Set Difference
One important difference is the list of instructions. All processors are told what do by programs or software using a instruction set and it influences the construction of processors and how they handle computing. Today, they are two main commercial instruction sets: CISC or Complex Instruction Set Computing and RISC or Reduced Instruction Set Computing. Let's see a brief description of both.
What is CISC?
Complex computing favors a simpler software approach by reducing the length of code and less usage of memory or RAM, which in turn sacrifices the build of a processor, resulting in higher power consumption.
What is RISC?
Reduced computing favors a simple hardware approach by reducing the clock cycles required for each instruction and the unpredictability of them, which in turn sacrifices the programming simplicity, resulting in higher RAM usage and harder-to-program software.
Typical but precise RISC vs CISC example: Multiply 2 numbers
To understand how each architecture philosophy differ from each other, it is better to use a simple and short example. If you require a processor to multiple 2 numbers, which instructions would you have to use? Let's start by defining the parts of the processor required for this example.
- The Main Memory is were the variables are located in memory modules (RAM). Learn more.
- The Registers store data pulled from the memory into a buffer of the processor. Learn more.
- The Execution Unit is in charge of logic operations to accomplish the math. Learn more.
The main memory has 6 rows and 4 columns. There is only 6 registers to store data, from ‘A' to ‘F'. Position are referred as row:column. Now, let's say that we have to multiply the numbers 1:2 and 5:3 and store the result in 2:4.
How they differentiate
Usage of RAM
CISC processors are constructed in a way they understand fewer lines of assembly codes. The complex instructions are stored in the hardware and the compiler doesn't do too much effort into translating to assembly. Therefore, less RAM is occupied. Here is the command for multiplication.
mult 1:2, 5:3RISC processors, on the other hand, focuses on simpler hardware construction and the lines of code has to be explicitly told what to load and store, step-by-step. Because there is more lines of code, more RAM is required. The compiler also has a harder time to convert higher language code into assembly.
load A, 1:2
load B, 5:3
prod A, B
store 2:4, A
Pipelining and Out-of-Order Execution
Since the instructions in RISC complete in equal amounts of time, pipelining is achievable and parallel processing helps get things done quicker. CISC is not able to perform this effectively.
Out-of-order execution reduces drastically idle time in a processor. It is a complicated topic for one blog post, so click here to learn more about this topic.
Instruction Length and Decoders
Decoders inside the processor are in charge of translating the instructions into operations. RISC have the advantage of having a predictable and fixed instruction length. Some architectures of RISC have 4 bytes in length. In CISC however, it varies from 1 to 15 bytes in length.
How does this affect the decoders? If they are unable to identify each instruction instantly, they are going to analyze all the incoming code searching for instruction, or even worse, guessing. This process of course, penalizes performance. The decoders have an easier task analyzing RISC instructions since they know that every 4 bytes, there is a new instruction. This is not the case with CISC because instructions have a variable and unpredictable length.
Buffers are temporary memory to store the registers used for the operations. Bigger buffer equals to higher out-of-order execution operation capability. In RISC it is possible to add more decoders easily (like in the M1) whereas in CISC, there is a practical limit already reached.
Power and Heat
Hardware construction on CISC processors are more complex and requieres more transistors to operate. Multiple cycles are required for every operation; in fact, many multiplications on CISC requires more operations than on RISC if they reutilize some the variables. Now, when we account for millions of operations that occurs every second, we begin to see a problem. This translates in more power consumption and therefore more heat to dissipate, which are two big problems.
Summarizing
The advantages of RISC over CISC can be displayed on this table for quick reference.
| RISC | CISC | |
|---|---|---|
| Length of instructions | Fixed and predictable. | Variable and unpredictable. |
| Clock Cycles | Single-clock instructions. | Multi-clock instructions. |
| Code length | Longer. | Shorter. |
| Transistors storage | Some stores memory registers. | Some stores complex instructions. |
| Instructions per line of code | One. | Multiple. |
| RAM Usage | Higher per program. | Lower per program. |
| Software approach | Easier for machines, harder for humans. | Easier for humans, harder for machines. |
| Hardware approach | Simple. | Complex. |
Resources
Take a look to the websites where I got this information.
- RISC vs CISC, Stanford University. Link.
- OCR A'Level (H046-H446) CISC vs RISC, Craig'n'Dave. Link.
- RISC vs CISC, Group Project for CPSC 355. Link.
- How Apple Just Changed the Entire Industry, ColdFusion. Link.
- Why Apple's M1 Chip is So Fast. The Dev Doctor. Link.
- Reduced instruction set computer in Wikipedia. Link.
- Complex instruction set computer in Wikipedia. Link.
- Instruction set architecture in Wikipedia. Link.
Where to buy
If you are considering to buy a CISC or RISC processor, click in one of links below.
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